A synchronous digital circuit, such as a central processing unit (CPU) or a digital signal processor (DSP), for example, requires a clock signal to coordinate timing of logic in the circuit. A frequency of the clock signal controls a switching speed or rate of the logic, and thus the performance of the circuit. A relationship exists between a clock frequency of the circuit and a voltage level powering the circuit. An increase in the clock frequency causes a corresponding increase in a minimum voltage level required to power the circuit for proper operation. Accordingly, an increase in clock frequency generally results in increased power consumption. Power consumption of the circuit can be decreased by lowering the voltage level. However, a reduction in voltage level decreases a maximum clock frequency possible for the circuit. The voltage level can be reduced until a minimum threshold voltage level necessary for proper operation of the circuit at a desired clock frequency is reached. To optimize power consumption while still providing acceptable performance, dynamic clock voltage scaling (DCVS) circuits can be employed in processor-based electronic devices, including user-based portable electronic devices. DCVS circuits control clock frequency and voltage level settings by predicting optimal clock frequency and voltage settings for a processor and/or other synchronously clocked components based on performance demands of the electronic device. In this manner, DCVS circuits may optimize power consumption required for a demanded performance level. Further information such as temperature, battery level, and operating system scheduler state can also be used to influence the manner in which DCVS circuits operate.
However, existing techniques that use operating system scheduler states to make DCVS decisions tend to fall short in the ability to account for significant variations in program runtime characteristics. For example, programs generally display two types of phase behaviors: (i) memory intensive phases and (ii) compute intensive phases. In memory intensive phases, the processor waiting on data from the memory subsystem tends to dominate execution time, whereas the processor is typically active during compute intensive phases and utilizing the available processor (non-memory-subsystem) resources to maximize computation. In general, the duration of the memory intensive phases and the compute intensive phases depends upon program characteristics. In some workloads, there can be a long memory bound phase where the processor is primarily waiting for the data and sitting idle. In such phases, voltage and clock frequency can be scaled down to reduce power and energy consumption. However, in most known processors, the operating system software typically makes decisions about whether and/or when to reduce voltage and frequency on a very coarse time granularity. For example, to make DCVS decisions, operating systems typically sample processor activity in the range of every tens to hundreds of milliseconds. From the operating system perspective, during program phases that last a smaller duration than the operating system sampling window, the processor is assumed to be active and doing useful work even if the processor is actually waiting on data to be retrieved from the memory subsystem. Accordingly, in reality, there may be pockets of opportunity to optimize power consumption without compromising performance where the processor is not active. The operating system tends to miss these power and energy saving opportunities and therefore cannot provide fine-grained DCVS control due to having a limited resolution in terms of reaction time as well as lacking visibility into hardware behavior (e.g., when the processor is stalled due to a last-level cache miss, the processor appears to be active and doing useful work from the operating system perspective).